1. Technical Field
The claimed invention relates generally to semiconductor products and more specifically to the selective etching of high aspect ratio openings using a single mask layer.
2. Description of Related Art
In the manufacture of semiconductor devices, individual components must be interconnected to perform functions. Generally, this is accomplished by the introduction of conductive materials into openings in the silicon substrate between the individual components.
A common process by which such interconnections are made is the damascene technique, whereby openings are selectively etched into a dielectric layer covering the individual components. Generally, a photoresist material is layered onto the dielectric layer and a pattern of openings outlined in the photoresist layer using lithographic techniques. An anisotropic etch is then used to form the openings in the dielectric layer. The photoresist material is then removed. Where openings are to connect individual components on more than one level, it is necessary to selectively cover some openings with an etch-resistant mask layer, etch the dielectric layer, and remove the mask layer. Generally, such a process requires the use of more than one mask layer with varying resistances to the anisotripic etch processes. Finally, the openings are filled with a conductive material, completing the connections between the individual components.
As the size of semiconductor devices has decreased, the width of the openings connecting them has necessarily decreased. As a result, it has become more difficult to fill high aspect ratio openings with the conductive material. There have been several inventions directed toward solving this problem. See, e.g., U.S. Pat. No. 6,710,447 to Nogami.
What has not been previously described, however, is the utilization of the high aspect ratio problem in selectively etching openings of varying depths in a dielectric layer, thereby eliminating the need for multiple mask layers.